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| the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit document no. s17998ej4v0ds00 (4th edition) date published march 2007 ns cp (n) printed in japan data sheet 2006 the mark " data sheet s17998ej4v0ds 2 inta0 pci bus pci bus interface arbiter ohci host controller ehci host controller root hub phy usb bus port 1 port 2 port 3 pme0 wakeup_event wakeup_event smi0 data sheet s17998ej4v0ds 3 pci bus interface : handles 32-bit 33 mhz pci bus ma ster and target function which comply with pci specification revision 2.2. the number of enabled ports is se t by bit in configuration space. arbiter : arbitrates among two ohci host cont roller cores and one ehci host controller core. ohci host controller : handles full- ( 12 mbps)/low-speed (1.5 mbps) signaling. ehci host controller : handles high- (480 mbps) signaling. root hub : handles usb hub function in host cont roller and controls connec tion (routing) between host controller core and port. phy : consists of high-speed transceiver, full- /low-speed transceiver, serializer, deserializer, etc. inta0 : is the pci interrupt si gnal for ohci host controller. smi0 : is the interrupt signal which is specif ied by open host controller interface specification for usb release 1.0a and enhanced host controller interface specification revision 1.0. the smi signal of each ohci host controlle r and ehci host controller appears at this signal. pme0 : is the interrupt signal which is s pecified by pci-bus pow er management interface specification revision 1.1. wakeup signal of each host controller core appears at this signal. data sheet s17998ej4v0ds 4 ? 120-pin plastic tqfp (fine pitch) (14 14) pd720102gc-yeb-a top view v dd v dd15 testen xt1/sclk xt2 vccrst0 smi0 pme0 pclk vbbrst0 v dd v ss inta0 n.c. n.c. gnt0 req0 ad31 ad30 v ss ad29 ad28 ad27 ad26 ad25 ad24 cbe30 idsel v dd dm1 v dd15 dp1 dm2 dp2 hsmode dm3 v dd v dd v dd v dd v dd dp3 clksel v dd n.c. v ss v ss v ss v ss v ss v ss v ss v ss v ss ad7 cbe00 ad8 ad9 ad10 ad11 ad12 v dd ad13 ad14 ad15 v ss cbe10 par serr0 perr0 stop0 devsel0 trdy0 irdy0 frame0 cbe20 ad16 ad17 ad18 v dd ad19 ad20 ad21 ad22 ad23 v ss v ss v dd av dd15 av dd33 rref n.c. n.c. av ss av ss (r) test3 test4 vdd15out v ss ppon3 ppon2 v ss v dd15 oci30 oci20 ppon1 oci10 srmod srclk srdta crun0 ad0 ad1 ad2 ad3 ad4 ad5 ad6 v dd v dd 1 5 10 15 20 25 35 30 40 50 55 45 60 65 70 85 90 75 80 95 100 105 110 115 120 data sheet s17998ej4v0ds 5 ? 120-pin plastic tqfp (fine pitch) (14 14) pd720102gc-yeb-a pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 ppon1 31 v ss 61 v dd15 91 clksel 2 oci20 32 ad23 62 ad12 92 hsmode 3 v ss 33 ad22 63 ad11 93 testen 4 ppon2 34 ad21 64 ad10 94 av ss (r) 5 oci30 35 ad20 65 v dd 95 rref 6 ppon3 36 ad19 66 ad9 96 av dd33 7 v dd 37 v dd 67 ad8 97 av dd15 8 vccrst0 38 ad18 68 cbe00 98 av ss 9 pme0 39 v ss 69 n.c. 99 v ss 10 n.c. 40 ad17 70 ad7 100 v dd15 11 pclk 41 ad16 71 v ss 101 dm1 12 v ss 42 cbe20 72 ad6 102 dp1 13 vbbrst0 43 frame0 73 ad5 103 v ss 14 inta0 44 irdy0 74 ad4 104 v ss 15 gnt0 45 v ss 75 v dd 105 dm2 16 req0 46 n.c. 76 ad3 106 dp2 17 ad31 47 trdy0 77 ad2 107 v dd 18 v dd 48 v dd 78 ad1 108 v dd 19 ad30 49 devsel0 79 ad0 109 dm3 20 ad29 50 stop0 80 v ss 110 dp3 21 v ss 51 perr0 81 xt1/sclk 111 v ss 22 ad28 52 serr0 82 n.c. 112 v dd 23 ad27 53 par 83 xt2 113 n.c. 24 ad26 54 v ss 84 v dd 114 v ss 25 ad25 55 cbe10 85 crun0 115 vdd15out 26 ad24 56 ad15 86 smi0 116 v dd 27 v dd 57 v dd 87 v ss 117 v dd 28 cbe30 58 ad14 88 srclk 118 test4 29 idsel 59 ad13 89 srmod 119 test3 30 v dd15 60 v ss 90 srdta 120 oci10 remark av ss (r) should be used to connect rref through 1 % precision reference resistor of 1.6 k . data sheet s17998ej4v0ds 6 ? 121-pin plastic fbga (8 8) pd720102f1-ca7-a bottom view 21 22 23 24 25 26 27 28 29 30 31 11 20 57 58 59 60 61 62 63 64 65 32 10 19 56 85 86 87 88 89 90 91 66 33 9 18 55 84 105 106 107 108 109 92 67 34 8 17 54 83 104 117 118 119 110 93 68 35 7 16 53 82 103 116 121 120 111 94 69 36 6 15 52 81 102 115 114 113 112 95 70 37 5 14 51 80 101 100 99 98 97 96 71 38 4 13 50 79 78 77 76 75 74 73 72 39 3 12 49 48 47 46 45 44 43 42 41 40 2 11 10 9 8 7 6 5 4 3 2 1 1 l k j h g f e d c b a data sheet s17998ej4v0ds 7 ? 121-pin plastic fbga (8 8) pd720102f1-ca7-a pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 dp3 32 rref 63 v ss 94 v dd 2 ppon1 33 v dd15 64 smi0 95 vdd15out 3 oci30 34 dm1 65 av ss (r) 96 test3 4 vccrst0 35 dp1 66 av dd33 97 v dd 5 pclk 36 v ss 67 v ss 98 v dd 6 gnt0 37 dm2 68 v ss 99 v dd 7 ad30 38 dp2 69 v ss 100 v dd 8 ad28 39 v dd 70 v ss 101 v dd15 9 ad25 40 dm3 71 v ss 102 v dd15 10 cbe30 41 test4 72 v ss 103 v ss 11 v ss 42 oci20 73 oci10 104 v ss 12 ad23 43 ppon3 74 ppon2 105 v dd15 13 ad21 44 pme0 75 vbbrst0 106 v dd15 14 ad18 45 inta0 76 ad31 107 v ss 15 cbe20 46 req0 77 ad27 108 v ss 16 trdy0 47 ad29 78 idsel 109 v ss 17 stop0 48 ad26 79 v ss 110 av ss 18 par 49 ad24 80 ad19 111 v dd 19 ad14 50 ad22 81 ad16 112 v dd 20 v ss 51 ad20 82 irdy0 113 v dd 21 ad12 52 ad17 83 serr0 114 v ss 22 ad11 53 frame0 84 cbe10 115 v ss 23 cbe00 54 devsel0 85 ad9 116 v dd 24 ad6 55 perr0 86 ad8 117 v dd 25 ad3 56 ad15 87 ad4 118 v dd 26 ad1 57 ad13 88 ad0 119 v dd 27 xt1/sclk 58 ad10 89 crun0 120 v dd 28 xt2 59 ad7 90 sclk 121 v dd 29 srmod 60 ad5 91 srdta 30 hsmode 61 ad2 92 clksel 31 testen 62 v ss 93 avdd15 remark av ss (r) should be used to connect rref through 1 % precision reference resistor of 1.6 k . data sheet s17998ej4v0ds 8 pin information (1/2) pin name i/o normal (test) buffer type active level function ad (31:0) i/o 3.3 v pci i/o with or input pci ?ad [31:0]? signal cbe (3:0)0 i/o 3.3 v pci i/o with or input pci ?c/be [3:0]? signal par i/o 3.3 v pci i/o with or input pci ?par? signal frame0 i/o 3.3 v pci i/o with or input low pci ?frame#? signal irdy0 i/o 3.3 v pci i/o with or input low pci ?irdy#? signal trdy0 i/o 3.3 v pci i/o with or input low pci ?trdy#? signal stop0 i/o 3.3 v pci i/o with or input low pci ?stop#? signal idsel i 3.3 v pci input with or input high pci ?idsel? signal devsel0 i/o 3.3 v pci i/o with or input low pci ?devsel#? signal req0 o (i/o) 3.3 v pci i/o with or input low pci ?req#? signal gnt0 i 3.3 v pci input with or input low pci ?gnt#? signal perr0 i/o 3.3 v pci i/o with or input low pci ?perr#? signal serr0 o (i/o) 3.3 v pci i/o with or input note 1 low pci ?serr#? signal inta0 o (i/o) 3.3 v pci i/o with or input note 1 low pci ?inta#? signal pclk i 3.3 v pci input with or input pci ?clk? signal vbbrst0 i 3.3 v schmitt input low pci ?rst#? signal crun0 i/o 3.3 v pci i/o with or input low pci ?clkrun#? signal pme0 o n-ch open drain buffer low pci ?pme#? signal vccrst0 i 3.3 v schmitt input low pci ?rst#? signal for d3 cold support smi0 o (i/o) 3.3 v i/o buffer low system management interrupt output xt1/sclk i osc block system clock input or oscillator in xt2 o osc block oscillator out clksel i 3.3 v input input clock frequency select signal hsmode i 3.3 v input high hype r-speed transfer mode enable signal srclk o (i/o) 3.3 v i/o buffer serial rom clock out srdta i/o 3.3 v i/o buffer serial rom data srmod i 3.3 v input with pull down re sistor high serial rom input enable testen note 2 i 3.3 v input with pull down resistor high test enable pin test3 note 2 i 3.3 v input with pull down resistor high test control test4 note 2 i 3.3 v input with pull down resistor high test control notes 1. these signals become n-ch open drai n buffers in normal operation. 2. these pins must be open on board. data sheet s17998ej4v0ds 9 (2/2) pin name i/o normal (test) buffer type active level function oci (3:1)0 i (i/o) 3.3 v i/o buffer with or input low usb port?s overcurrent status input ppon (3:1) o (i/o) 3.3 v i/o buffer high usb port?s power supply control output dp (3:1) i/o usb high speed d + i/o usb high speed d + signal dm (3:1) i/o usb high speed d ? i/o usb high speed d ? signal rref a analog reference resistor vdd15out o internal regulator output 1. 5 v voltage output from internal regulator v dd15 1.5 v v dd from vdd15out v dd 3.3 v v dd av dd15 1.5 v v dd for analog circuit av dd33 3.3 v v dd for analog circuit v ss v ss av ss v ss for analog circuit av ss (r) v ss for rref circuit n.c. no connection remark the signal marked as ?(i/o)? in t he above table operates as i/o signals dur ing testing. however, they do not need to be considered in normal use. data sheet s17998ej4v0ds 10 how to connect to external elements 2.1 handling unused pins to realize less than 3 ports host contro ller implementation, appropriate value s hall be set to port no field in ext1 register. and unused pins sha ll be connected as shown below. table 2-1. unused pin connection pin direction connection method dpx i/o no connection (open) dmx i/o no connection (open) ocix i ?h? clamp pponx o no connection (open) 2.2 usb port connection figure 2?1. usb downstream port connection dmn dpn downstream port usb a receptacle connector from power switch output 1 2 3 4 gnd pd720102 d ? d+ vbus data sheet s17998ej4v0ds 11 pd720102 2.3 internal regulator circuit connection figure 2?2. internal regulator circuit connection dd15 dd15 dd15 3.3 f (ceramic type only) caution vdd15out must be routed to only v dd15 (and av dd15 ). in case that vdd15o ut is also used for power supply of other ics, this may cause unstable operation of the ?pd720102. remark v dd15 is powered by vdd15out from internal regulator. it is not necessary to use external regulator for v dd15 . 2.4 analog circuit connection figure 2?3. analog circuit connection 1.6 k + 1 % ? remark the board layout should minimize the total pat h length from rref through the resistor to av ss (r) and path length to av ss (analog ground). av ss must be stable. data sheet s17998ej4v0ds 12 crystal connection figure 2?4. crystal connection crystal the following crystals are evaluated on our reference design board. table 2- 2 shows the external parameters. table 2-2. external parameters vender crystal r c1 c2 kds note 1 at-49 30.000 mhz 100 12 pf 12 pf ndk note 2 at-41 30.000 mhz 470 10 pf 10 pf notes 1. daishinku corp. 2. nihon dempa kogyo co., ltd. in using these crystals, contact kd s or ndk to get the specification on external components to be used in conjunction with the crystal. kds's home page: http://www. kds.info/english.html ndk's home page: http://www.ndk.com/ data sheet s17998ej4v0ds 13 external serial rom connection figure 2?5. external serial rom connection 3.3 v 1.5 k the following serial rom is us ed on our reference design board. table 2-3. external parameters vender product name size atmel corporation at24c01a-10sc-2.7 128 bytes srmod/srclk/srdta can be opened, when seri al rom is not necessary on board. data sheet s17998ej4v0ds 14 electrical specifications 3.1 buffer list ? 3.3 v input buffer clksel, hsmode ? 3.3 v input buffer with pull down resistor srmod, testen, test3, test4 ? 3.3 v input schmitt buffer vbbrst0, vccrst0 ? 3.3 v i ol = 9 ma bi-directional buffer smi0, ppon(3:1), srclk, srdta ? 3.3 v i ol = 9 ma bi-directional buffer with enable (or type) oci(3:1)0 ? 3.3 v pci input buffer with enable (or type) idsel, gnt0, pclk ? 3.3 v pci bi-directional buffer with enable (or type) ad(31:0), cbe(3:0)0, par, frame0, irdy0, trdy 0, stop0, devsel0, req0, perr0, serr0, inta0, crun0 ? n-ch open drain buffer pme0 ? 3.3 v oscillator interface xt1/sclk, xt2 ? usb interface, analog signal dp(3:1), dm(3:1), rref data sheet s17998ej4v0ds 15 terminology terms used in absolute maximum ratings parameter symbol meaning power supply voltage v dd , v dd15, av dd33 , av dd15 indicates the voltage range within which damage or reduced reliability will not result when power is applied to a v dd pin. input voltage v i indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. output voltage v o indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. output current i o indicates absolute tolerance values for dc current to prevent damage or reduced reliability when current flows out of or into output pin. operating ambient temperature t a indicates the ambient temperatur e range for normal logic operations. storage temperature t stg indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current is applied to the device. terms used in recomme nded operating range parameter symbol meaning power supply voltage v dd , av dd33 indicates the voltage range for normal logic operations occur when v ss = 0 v. high-level input voltage v ih indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * if a voltage that is equal to or greater than the ?min.? value is applied, the input voltage is guaranteed as high level voltage. low-level input voltage v il indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * if a voltage that is equal to or lesser than the ?max.? value is applied, the input voltage is guaranteed as low level voltage. hysteresis voltage v h indicates the differential between t he positive and the negative trigger voltage. input rise time t ri indicates allowable input rise time to input signal transition time from 0.1 x v dd to 0.9 x v dd . input fall time t fi indicates allowable input fall time to input signal transition time from 0.9 x v dd to 0.1 x v dd . data sheet s17998ej4v0ds 16 parameter symbol meaning off-state output leakage current i oz indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. input leakage current i i indicates the current that flows when t he input voltage is supplied to the input pin. low-level output current i ol indicates the current that flows to the output pins when the rated low-level output voltage is being applied. high-level output current i oh indicates the current that flows from the output pins when the rated high-level output voltage is being applied. data sheet s17998ej4v0ds 17 electrical specifications absolute maximum ratings parameter symbol condition rating unit v dd , av dd33 ? 0.5 to + 4.6 v power supply voltage v dd15 , av dd15 ? 0.5 to + 2.0 v input voltage, 3.3 v buffer v i v i < v dd + 0.5 v ? 0.5 to + 4.6 v output voltage, 3.3 v buffer v o v o < v dd + 0.5 v ? 0.5 to + 4.6 v 3.3 v buffer (i ol = 9 ma) 29 ma output current i o pci buffer 58 ma operating ambient temperature t a ? 20 to + 70 c storage temperature t stg ? 40 to + 125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. that is, the absolute maximum ratings are rated valu es at which the product is on the verge of suffering physical damage , and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. the ratings and conditions indicated for dc ch aracteristics and ac characteristics represent the quality assurance range dur ing normal operation. recommended operating ranges parameter symbol condition min. typ. max. unit operating voltage v dd , av dd33 3.135 3.3 3.465 v vbbrst0, vccrst0 2.4 v dd v high-level input voltage 3.3 v high-level input voltage v ih other input pins 2.0 v dd v vbbrst0, vccrst0 0 0.6 v low-level input voltage 3.3 v low-level input voltage v il other input pins 0 0.8 v hysteresis voltage 3.3 v hysteresis voltage v h 0.3 1.5 v input rise time normal buffer 0 200 ns schmitt buffer t ri 0 10 ms input fall time normal buffer 0 200 ns schmitt buffer t fi 0 10 ms data sheet s17998ej4v0ds 18 ? 20 to + 70 c) control pin block parameter symbol condition min. max. unit off-state output current i oz v o = v dd or v ss 10 a low-level output current 3.3 v low-level output current (9 ma) i ol v ol = 0.4 v 9.0 ma high-level output current 3.3 v high-level output current (9 ma) i oh v oh = 2.4 v ? 9.0 ma input leakage current 3.3 v buffer v i = v dd or v ss 10 a 3.3 v buffer with pull down resistor i i v i = v dd 175 a pci interface block parameter symbol condition min. max. unit high-level input voltage v ih 0.5v dd v dd +0.5 v low-level input voltage v il ?0.5 0.3v dd v low-level output current i ol v ol = 0.1v dd 1.5 ma high-level output current i oh v oh = 0.9v dd ?0.5 ma input leakage current i il 0 < v in < v dd 10 a pme0 leakage current i off v o < 3.6 v v dd off or floating 1 a data sheet s17998ej4v0ds 19 parameter symbol conditions min. max. unit output pin impedance z hsdrv 40.5 49.5 input levels for low-/full-speed: high-level input voltage (drive) v ih 2.0 v high-level input voltage (floating) v ihz 2.7 3.6 v low-level input voltage v il 0.8 v differential input sensitivity v di ? (d + ) ? (d ? ) ? 0.2 v differential common mode range v cm includes v di range 0.8 2.5 v output levels for low-/full-speed: high-level output voltage v oh r l of 14.25 k to gnd 2.8 3.6 v low-level output voltage v ol r l of 1.425 k to 3.6 v 0.0 0.3 v se1 v ose1 0.8 v output signal crossover point voltage v crs 1.3 2.0 v input levels for high-speed: high-speed squelch detection threshold (differential signal) v hssq 100 150 mv high-speed disconnect det ection threshold (differential signal) v hsdsc 525 625 mv high-speed data signaling common mode voltage range v hscm ? 50 + 500 mv high-speed differential input signaling level see figure 3?2 . output levels for high-speed: high-speed idle state v hsoi ? 10 + 10 mv high-speed data signaling high v hsoh 360 440 mv high-speed data signaling low v hsol ? 10 + 10 mv chirp j level (differential signal) v chirpj 700 1100 mv chirp k level (differential signal) v chirpk ? 900 ? 500 mv data sheet s17998ej4v0ds 20 4.6 ? 1.0 input voltage range (v) differential input voltage range differential output crossover voltage range 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 figure 3?2. receiver sensitivity for transceiver at dp/dm 0 v differential + 400 mv differential ? 400 mv differential unit interval level 1 level 2 0% 100% point 5 point 2 point 1 point 3 point 4 point 6 figure 3?3. receiver measurement fixtures vbus d + d ? gnd 15.8 + to 50 inputs of a high speed differential oscilloscope, or 50 outputs of a high speed differential data generator ? 50 coax 50 coax usb connector nearest device test supply voltage 15.8 143 143 data sheet s17998ej4v0ds 21 with 30 mhz crystal with 48 mhz oscillator parameter symbol condition typ. max. typ. max. unit p wd0-0 device state = d0, all the ports does not connect to any function, and each ohci cont roller is under usb suspend and ehci controller is stopped. note 1 11.0 16.0 3.0 7.0 ma the power consumption under the state without suspend. device state = d0, the number of active ports is 1. note 2 p wd0-1 full- or low-speed device is on the port. high-speed device is on the port. 15.6 60.3 22.6 70.8 7.7 60.7 13.5 71.3 ma ma the power consumption under the state without suspend. device state = d0, the number of active ports is 2. note 2 p wd0-2 full- or low-speed devices are on the port. high-speed devices are on the port. 17.4 96.1 31.6 111.8 9.5 96.6 22.4 112.4 ma ma the power consumption under the state without suspend. device state = d0, the number of active ports is 3. note 2 p wd0-3 full- or low-speed devices are on the port. high-speed devices are on the port. 18.8 130.7 40.0 151.8 10.8 131.2 31.5 152.2 ma ma p wd0_c the power consumption under suspend state during pci clock is stopped by crun0. device state = d0. 11.0 16.0 3.0 7.0 ma p wd1 device state = d1, analog pll output is stopped. note 3 2.1 5.9 3.0 7.0 ma p wd2 device state = d2, analog pll output is stopped. note 3 2.1 5.9 3.0 7.0 ma p wd3h device state = d3 hot , vccrst0 = high, analog pll output is stopped. note 3 2.1 5.9 3.0 7.0 ma power consumption p wd3c device state = d3 cold , vccrst0 = low. note 4 0.03 3.0 1.38 5.2 ma notes 1. when any device is not connected to all the ports of hc, the pow er consumption for hc does not depend on the number of active ports. 2. the number of active ports is set by the value of po rt no field in pci configuration space ext register. 3. this is the case when pci bus state is b0. 4. this is the case when pci bus state is b3. remark these are estimated value on windows? xp environment. pin capacitance parameter symbol condition min. max. unit input capacitance c i 8 pf output capacitance c o 8 pf i/o capacitance c io 8 pf pci input pin capacitance c in 8 pf pci clock input pin capacitance c clk 8 pf pci idsel input pin capacitance c idsel v dd = 0 v, t a = 25c f c = 1 mhz unmeasured pins returned to 0 v 8 pf data sheet s17998ej4v0ds 22 ? 20 to + 70 c) system clock ratings parameter symbol condition min. typ. max. unit crystal ? 500 ppm 30 + 500 ppm mhz clock frequency f clk oscillator block ? 500 ppm 48 + 500 ppm mhz clock duty cycle t duty 40 50 60 % remarks 1. recommended accuracy of clock frequency is 100 ppm. 2. required accuracy of crystal or oscillator block is including initial frequency accuracy, the spread of crystal capacitor loading, supply vo ltage, temperature, and aging, etc. pci interface block parameter symbol condition min. max. unit pci clock cycle time t cyc 30 33 ns pci clock pulse, high-level width t high 11 ns pci clock pulse, low-level width t low 11 ns pci clock, rise slew rate s cr 0.2v dd to 0.6v dd 1 4 v/ns pci clock, fall slew rate s cf 0.2v dd to 0.6v dd 1 4 v/ns pci reset active time (vs. power supply stability) t rst 1 ms pci reset active time (vs. clk start) t rst-clk 100 s output float delay time (vs. rst0 ) t rst-off 40 ns pci reset rise slew rate s rr 50 mv/ns pci bus signal output time (vs. pclk ) t val 2 11 ns pci point-to-point signal output time (vs. pclk ) t val (ptp) req0 2 12 ns output delay time (vs. pclk ) t on 2 ns output float delay time (vs. pclk ) t off 28 ns input setup time (vs. pclk ) t su 7 ns point-to-point input setup time (vs. pclk ) t su (ptp) gnt0 10 ns input hold time t h 0 ns data sheet s17998ej4v0ds 23 (1/2) parameter symbol conditions min. max. unit low-speed source electrical characteristics rise time (10 to 90%) t lr c l = 200 to 600 pf, r s = 36 75 300 ns fall time (90 to 10%) t lf c l = 200 to 600 pf, r s = 36 75 300 ns differential rise and fall time matching t lrfm (t lr /t lf ) 80 125 % low-speed data rate t ldraths average bit rate 1.49925 1.50075 mbps source jitter total (including frequency tolerance): to next transition for paired transitions t ddj1 t ddj2 ? 25 ? 14 + 25 + 14 ns ns source jitter for differential transition to se0 transition t ldeop ? 40 + 100 ns receiver jitter: to next transition for paired transitions t ujr1 t ujr2 ? 152 ? 200 + 152 + 200 ns ns source se0 interval of eop t leopt 1.25 1.50 s receiver se0 interval of eop t leopr 670 ns width of se0 interval during differential transition t fst 210 ns full-speed source electrical characteristics rise time (10 to 90%) t fr c l = 50 pf 4 20 ns fall time (90 to 10%) t ff c l = 50 pf 4 20 ns differential rise and fall time matching t frfm (t fr /t ff ) 90 111.11 % full-speed data rate t fdraths average bit rate 11.9940 12.0060 mbps frame interval t frame 0.9995 1.0005 ms consecutive frame interval jitter t rfi no clock adjustment 42 ns source jitter total (including frequency tolerance): to next transition for paired transitions t dj1 t dj2 ? 3.5 ? 4.0 + 3.5 + 4.0 ns ns source jitter for differential transition to se0 transition t fdeop ? 2 + 5 ns receiver jitter: to next transition for paired transitions t jr1 t jr2 ? 18.5 ? 9 + 18.5 + 9 ns ns source se0 interval of eop t feopt 160 175 ns receiver se0 interval of eop t feopr 82 ns width of se0 interval during differential transition t fst 14 ns data sheet s17998ej4v0ds 24 (2/2) parameter symbol conditions min. max. unit high-speed source electrical characteristics rise time (10 to 90%) t hsr 500 ps fall time (90 to 10%) t hsf 500 ps driver waveform see figure 3?4 . high-speed data rate t hsdrat 479.760 480.240 mbps microframe interval t hsfram 124.9375 125.0625 s consecutive microframe interval difference t hsrfi 4 high- speed bit times data source jitter see figure 3?4 . receiver jitter tolerance see figure 3?2 . hub event timings time to detect a downstream facing port connect event t dcnn 2.5 2000 s time to detect a disconnect event at a hub?s downstream facing port t ddis 2.0 2.5 s duration of driving resume to a downstream port t drsmdn nominal 20 ms time from detecting downstream resume to rebroadcast t ursm 1.0 ms inter-packet delay for packets traveling in same direction for high-speed t hsipdsd 88 bit times inter-packet delay for packets traveling in opposite direction for high-speed t hsipdod 8 bit times inter-packet delay for root hub response for high-speed t hsrspipd1 192 bit times time for which a chirp j or chirp k must be continuously detected during reset handshake t filt 2.5 s time after end of device chirp k by which hub must start driving first chirp k t wtdch 100 s time for which each individual chirp j or chirp k in the chir p sequence is driven downstream during reset t dchbit 40 60 s time before end of reset by which a hub must end its downstream chirp sequence t dchse0 100 500 s data sheet s17998ej4v0ds 25 0 v differential + 400 mv differential ? 400 mv differential unit interval level 1 level 2 0% 100% point 4 point 3 point 1 point 2 point 5 point 6 figure 3?5. transmitter measurement fixtures vbus d + d ? gnd 15.8 + to 50 inputs of a high speed differential oscilloscope, or 50 outputs of a high speed differential data generator ? 50 coax 50 coax usb connector nearest device test supply voltage 15.8 143 143 data sheet s17998ej4v0ds 26 timing diagram pci clock 0.4v dd 0.6v dd 0.2v dd 0.5v dd 0.3v dd 0.4v dd (ptp: min.) t cyc t high t low pci reset pclk pwr_good vbbrst0 100 ms (typ.) t rst t rst-off pci signals valid t rst-clk data sheet s17998ej4v0ds 27 pclk 0.4v dd 0.6v dd 0.2v dd output delay 3-state output delay 0.615v dd (for falling edge) 0.285v dd (for falling edge) t val , t val (ptp) t on t off pci input timing measurement condition pclk 0.4v dd 0.6v dd 0.2v dd input t su , t su (ptp) 0.6v dd 0.2v dd 0.4v dd t h data sheet s17998ej4v0ds 28 t period differential data lines crossover points consecutive transitions n t period + t xdj1 paired transitions n t period + t xdj2 usb differential-to-eop transition skew and eop width for low-/full-speed t period differential data lines crossover point crossover point extended source eop width: t feopt t leopt receiver eop width: t feopr t leopr diff. data-to- se0 skew n t period + t xdeop usb receiver jitter tolera nce for low-/full-speed differential data lines t period t xjr t xjr1 t xjr2 consecutive transitions n t period + t xjr1 paired transitions n t period + t xjr2 data sheet s17998ej4v0ds 29 d ? /d + d + /d ? v izh (min.) v il v ss device disconnected disconnect detected t ddis full-/high-speed device connect detection v ih v ss device connected connect detected d ? d + t dcnn low-speed device connect detection v ih v ss device connected connect detected d + d ? t dcnn data sheet s17998ej4v0ds 30 package drawings ? pd720102gc-yeb-a 90 60 61 120 1 31 30 91 s 120-pin plastic tqfp (fine pitch) (14x14) item millimeters i j 0.40 (t.p.) 0.07 a 16.00 0.20 f 1.20 g h 0.18 0.05 1.20 k 1.00 0.20 t 0.25 s 1.20max. r3 u 0.60 0.15 + 4 ? 3 r h k l j f n q m g i a b cd sm t u s p detail of lead end note each lead centerline is located within 0.07 mm of its true position (t.p.) at maximum material condition. b 14.00 0.20 c d 16.00 0.20 14.00 0.20 l 0.50 m 0.17 + 0.03 ? 0.07 n 0.08 p 1.00 0.05 q 0.10 0.05 p120gc-40-yeb-1 data sheet s17998ej4v0ds 31 ? pd720102f1-ca7-a item dimensions d e w a a1 a2 e 8.00 0.10 8.00 0.10 0.20 0.30 0.05 0.05 0.08 0.99 0.10 0.69 0.65 (unit:mm) 0.10 0.20 0.75 0.75 p121f1-65-ca7 s e y1 s a a1 a2 s y s x bab m s wb s wa zd ze index mark b a 1 2 3 4 5 6 7 8 9 10 11 a b c d e f g h j k l d e x y y1 zd ze b 0.40 121-pin plastic fbga (8x8) index mark data sheet s17998ej4v0ds 32 recommended soldering conditions the pd720102 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http ://www.necel.com/pkg/en/mount/index.html) ? pd720102gc-yeb-a: 120-pin plastic tq fp (fine pitch) (14 14) soldering method solder ing conditions symbol infrared reflow peak package?s surface temperat ure: 260 c, reflow time: 60 seconds or less (220 c or higher), maximum allowable number of reflow processes: 3, exposure limit note : 7 days (10 to 72 hours pre-backing is required at 125c afterwards), flux: rosin flux with low chlori ne (0.2 wt% or below) recommended. data sheet s17998ej4v0ds 33 data sheet s17998ej4v0ds 34 data sheet s17998ej4v0ds 35 waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 pd720102 the information in this document is current as of march, 2007. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": usb logo is a trademark of us b implementers forum, inc. windows is either a registered trad emark or a trademark of microsoft corporation in the united states and/or other countries. |
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